The Chips Are Stacked

Chris Lockfort is a fifth year student at the Rochester Institute of Technology studying Applied Networking & Systems Administration and Computer Engineering. This piece about emerging computer chip manufacturing methods is intended for the "gadget-loving-geek" audience, typical to someplace liked Wired or Slashdot for instance.

The Chips Are Stacked

How the Move to 3-D Chip Technology Changes the Processor Game

Chris Lockfort

Smaller, more battery-friendly cell phones. Cooler, more powerful desktop computers. More complex video processors. A gadget revolution is at hand.

Simplified, the computer chips of today are manufactured as a two-dimensional plane of transistors and interconnecting wires, all printed onto a piece of backing material (substrate) via a complex and delicate manufacturing process. This process is reaching its limits in several areas; in order to keep increasing the number of transistors per chip, chip manufacturers have been making smaller and smaller transistors. This has its side benefits; it takes less power to switch these tinier transistors. However, this planar approach has its issues; as the interconnecting wires between these transistors become smaller and smaller (only a few atoms thick in the latest revisions), there is more electrical resistance, and therefore, more heat is created, which can offset any heat savings garnered by needing less power to switch the transistors themselves. With transistors approaching their minimum possible size, it will become increasingly difficult to increase the number of transistors per chip in the future.

The solution is as deceptively simple as it is elegant; thinking three-dimensionally, one can stack multiple planes of transistors on top of each other, and connect them together. This design concept solves many of the problems with the previous architecture.

Some manufacturers are already taking steps into this area; in an early foray into the 3D chip making field, Intel will soon be mass-producing chips with a pseudo-3D architecture; all of the transistor logic will still be on the same two-dimensional slice, but a top layer is added to provide additional interconnect wires, in a bid to reduce heat output through lower electrical resistance. Memory manufacturers have been doing chip stacking (the process of stacking these multiple planes of transistors on top of each other) for some time to achieve the densities required for newer chips’ memory capacity.

While these applications have entered the market, they are not without their issues. The manufacturing process is delicate enough that in each wafer made, a few chips are expected to fail. This problem is compounded when multiple layers are used; if each layer has a chance of failing, then the chance that at least one part of the entire chip will be bad is multiplied, so even relatively high yields (90%+ good layers) can result in three-quarters of the final products having to be thrown out, which is obviously an expensive endeavor. And, while having more transistors per square inch of chip area is a good thing, this means more heat, and less area to dissipate it, requiring additional cooling, and bringing with it a slew of new problems.

There are many problems with this new chip stacking concept, but, pun not intended, the only way to go is up. As unrelated transistor switching problems have required a paradigm shift to CPUs with many slower cores, rather than a single fast CPU, there has arisen an electrical problem with interconnecting on-chip memory between these CPUs so that they may share data. Electrons must take a very arduous stop-and-go path through the huge field of on-die memory, much like a wave overflowing many locks on its way to a town, and by the time it reaches the processor logic, it is full of turbulence and missing most of its original push, an analogue to electrical properties of greatly increased capacitance and inductance.

There are high hopes for the technology going forward, with hopes for applications in creating even lower power chips, both via using multilayer technology for resistance reduction as Intel is currently, and by using the extra vertical space to scatter voltage regulators throughout the chip, the computer engineering equivalent of the plumbing practice of installing pressure regulators every few floors of a high building, so that the pressure required to reach the top floor does not cause poor lower-floor residents with jet-stream sinks and those at the top with barely a dribble. Another hoped future application is for memory much physically closer to the processing pipeline, both reducing the electrical problems described above, as well as reducing the latency required to access this memory, which should result in faster-performing processors.

Works Cited

Edwards, C. "Doing the 3D chip shuffle." Engineering & Technology (17509637) 6.9 (2011): 82-85. Business Source Elite. EBSCO. Web. 25 Oct. 2011.